Masahiro Fujita

Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita: Rectification of advanced microprocessors without changing routing on FPGAs (abstract only). FPGA 2013: 279

Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal: Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. VLSI Design 2013

Viacheslav Izosimov, Giuseppe Di Guglielmo, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Masahiro Fujita: Time-Constraint-Aware Optimization of Assertions in Embedded Software. J. Electronic Testing 28(4): 469-486 (2012)

Amir Masoud Gharehbaghi, Masahiro Fujita: Transaction Ordering in Network-on-Chips for Post-Silicon Validation. IEICE Transactions 95-A(12): 2309-2318 (2012)

Yasuyuki Kimura, Fabrice G. Siméon, Sami S. Zoghbi, Yi Zhang, Jun Hatazawa, Victor W. Pike, Robert B. Innis, Masahiro Fujita: Quantification of metabotropic glutamate subtype 5 receptors in the brain by an equilibrium method using ¹⁸F-SP203. NeuroImage 59(3): 2124-2130 (2012)

Paolo Zanotti-Fregonara, Christina S. Hines, Sami S. Zoghbi, Jeih-San Liow, Yi Zhang, Victor W. Pike, Wayne C. Drevets, Alan G. Mallinger, Carlos A. Zarate Jr., Masahiro Fujita, Robert B. Innis: Population-based input function and image-derived input function for [¹¹C](R)-rolipram PET imaging: Methodology, validation and application to the study of major depressive disorder. NeuroImage 63(3): 1532-1541 (2012)

Masahiro Fujita, Hiroaki Yoshida: Post-silicon patching for verification/debugging with high-level models and programmable logic. ASP-DAC 2012: 232-237

Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita: Automated data analysis techniques for a modern silicon debug environment. ASP-DAC 2012: 298-303

Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita: On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC 2012: 695-700

Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita: SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. ATS 2012: 19-24

Amir Masoud Gharehbaghi, Masahiro Fujita: Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods. ATS 2012: 143-148

Marco Bonato, Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli: Dynamic property mining for embedded software. CODES+ISSS 2012: 187-196

Masahiro Fujita: Simulation-Based Analysis of Cyberphysical Systems. DSD 2012: 485-492

Masahiro Fujita, Hiroaki Yoshida: Post-silicon debugging targeting electrical errors with patchable controllers (abstract only). FPGA 2012: 271

Amir Masoud Gharehbaghi, Masahiro Fujita: Automatic rectification of design errors in complex processors with programmable hardware. FPT 2012: 141-146

Shohei Ono, Takeshi Matsumoto, Masahiro Fujita: Automatic assertion extraction in gate-level simulation using GPGPUs. ICCD 2012: 522-523

Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita: SEU tolerant robust memory cell design. IOLTS 2012: 13-18

Amir Masoud Gharehbaghi, Masahiro Fujita: Transaction-based post-silicon debug of many-core System-on-Chips. ISQED 2012: 702-708

Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita: Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2^m and algebraic techniques. MEMOCODE 2012: 65-74

Masahiro Fujita: Future direction of digital content: 20th anniversary keynote talk. ACM Multimedia 2012: 1-2

Koji Nakamaru, Toru Matsuoka, Masahiro Fujita: Distance aware ray tracing for curves. SIGGRAPH Posters 2012: 103

Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita: SEU Tolerant Robust Latch Design. VDAT 2012: 223-232

Takeshi Matsumoto, Shohei Ono, Masahiro Fujita: An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence. VLSI-SoC 2012: 291-294

Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda: Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports 2(8): 57-73 (2012)

Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita: Multi-Level Bounded Model Checking with Symbolic Counterexamples. IEICE Transactions 94-A(2): 696-705 (2011)

Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita: An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging. IEICE Transactions 94-A(7): 1519-1529 (2011)

Paolo Zanotti-Fregonara, Sami S. Zoghbi, Jeih-San Liow, Elise Luong, Ronald Boellaard, Robert L. Gladding, Victor W. Pike, Robert B. Innis, Masahiro Fujita: Kinetic analysis in human brain of [¹¹C](R)-rolipram, a positron emission tomographic radioligand to image phosphodiesterase 4: A retest study and use of an image-derived input function. NeuroImage 54(3): 1903-1909 (2011)

Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan: Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. ARC 2011: 125-132

Masahiro Fujita: Utilizing high level design information to speed up post-silicon debugging. ASP-DAC 2011: 301-305

Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita: On-chip dynamic signal sequence slicing for efficient post-silicon debugging. ASP-DAC 2011: 719-724

Masahiro Fujita: High Level Verification and Its Use at Pos-Silicon Debugging and Patching. Asian Test Symposium 2011: 464-469

Masahiro Fujita: Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols. ATVA 2011: 43-50

Hiroaki Yoshida, Masahiro Fujita: An energy-efficient patchable accelerator for post-silicon engineering changes. CODES+ISSS 2011: 13-20

Viacheslav Izosimov, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Giuseppe Di Guglielmo, Masahiro Fujita: Optimization of Assertion Placement in Time-Constrained Embedded Systems. European Test Symposium 2011: 171-176

Ratna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan, S. K. Nandy: Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture. FPT 2011: 1-5

Bijan Alizadeh, Masahiro Fujita: Modular equivalence verification of polynomial datapaths with multiple word-length operands. HLDVT 2011: 9-16

Amir Masoud Gharehbaghi, Masahiro Fujita: Formal verification guided automatic design error diagnosis and correction of complex processors. HLDVT 2011: 121-127

Hideo Tanida, Masahiro Fujita, Mukul R. Prasad, Sreeranga P. Rajan: Client-tier Validation of Dynamic Web Applications. ICSOFT (2) 2011: 86-95

Bijan Alizadeh, Masahiro Fujita: Early case splitting and false path detection to improve high level ATPG techniques. ISCAS 2011: 1463-1466

Amir Masoud Gharehbaghi, Masahiro Fujita: Global transaction ordering in Network-on-Chips for post-silicon validation. ISQED 2011: 284-289

Bijan Alizadeh, Masahiro Fujita: Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. ISQED 2011: 297-302

Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita: SEU tolerant SRAM cell. ISQED 2011: 597-602

Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli, Stefano Soffia: EFSM-based model-driven approach to concolic testing of system-level design. MEMOCODE 2011: 201-209

Virendra Singh, Masahiro Fujita: Tutorial: "Post silicon debug of SOC designs". SoCC 2011: 18

Hiroaki Yoshida, Masahiro Fujita: Performance-Constrained Transistor Sizing for Different Cell Count Minimization. JIP 18: 252-262 (2010)

William C. Kreisl, Masahiro Fujita, Yota Fujimura, Nobuyo Kimura, Kimberly J. Jenko, Pavitra Kannan, Jinsoo Hong, Cheryl L. Morse, Sami S. Zoghbi, Robert L. Gladding, Steven Jacobson, Unsong Oh, Victor W. Pike, Robert B. Innis: Comparison of [¹¹C]-(R)-PK 11195 and [¹¹C]PBR28, two radioligands for translocator protein (18 kDa) in human and monkey: Implications for positron emission tomographic imaging of this inflammation biomarker. NeuroImage 49(4): 2924-2932 (2010)

Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita: Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 737-748 (2010)

Bijan Alizadeh, Masahiro Fujita: Modular Datapath Optimization and Verification Based on Modular-HED. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1422-1435 (2010)

Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita: Pipelined Microprocessors Optimization and Debugging. ARC 2010: 435-444

Bijan Alizadeh, Masahiro Fujita: Guided gate-level ATPG for sequential circuits using a high-level test generation approach. ASP-DAC 2010: 425-430

Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita: Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. CASES 2010: 77-86

Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita: Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). FPGA 2010: 288

Bijan Alizadeh, Masahiro Fujita: A debugging method for repairing post-silicon bugs of high performance processors in the fields. FPT 2010: 328-331

Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita: SEU tolerant SRAM for FPGA applications. FPT 2010: 491-494

Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler: Polynomial datapath optimization using constraint solving and formal modelling. ICCAD 2010: 756-761

Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita: Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging. ICCD 2010: 402-408

Masahiro Fujita, Hideo Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto: Synthesis and formal verification of on-chip protocol transducers through decomposed specification. ISQED 2010: 515-523

Masahiro Fujita: Intelligence Dynamics: a concept and preliminary experiments for open-ended learning agents. Autonomous Agents and Multi-Agent Systems 19(3): 248-271 (2009)

Anmol Mathur, Masahiro Fujita, Edmund M. Clarke, Pascal Urard: Functional Equivalence Verification Tools in High-Level Synthesis Flows. IEEE Design & Test of Computers 26(4): 88-95 (2009)

Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita: Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath. IEICE Transactions 92-D(5): 972-984 (2009)

Bijan Alizadeh, Masahiro Fujita: A Unified Framework for Equivalence Verification of Datapath Oriented Applications. IEICE Transactions 92-D(5): 985-994 (2009)

Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. IEICE Transactions 92-A(6): 1464-1475 (2009)

O. Sarbishei, M. Tabandeh, Bijan Alizadeh, Masahiro Fujita: A Formal Approach for Debugging Arithmetic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 742-754 (2009)

Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita: A Post-Silicon Debug Support Using High-Level Design Description. Asian Test Symposium 2009: 137-142

Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi: Debugging from high level down to gate level. DAC 2009: 627-630

O. Sarbishei, Bijan Alizadeh, Masahiro Fujita: Polynomial datapath optimization using partitioning and compensation heuristics. DAC 2009: 931-936

Bijan Alizadeh, Masahiro Fujita: Modular arithmetic decision procedure with auto-correction mechanism. HLDVT 2009: 138-145

Bijan Alizadeh, Masahiro Fujita: Improved heuristics for finite word-length polynomial datapath optimization. ICCAD 2009: 739-744

Amir Masoud Gharehbaghi, Masahiro Fujita: Transaction-based debugging of system-on-chips with patterns. ICCD 2009: 186-192

Hiroaki Yoshida, Masahiro Fujita: Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences. ISQED 2009: 366-370

O. Sarbishei, M. Tabandeh, Bijan Alizadeh, Masahiro Fujita: High-level optimization of integer multipliers over a finite bit-width with verification capabilities. MEMOCODE 2009: 56-65

Masahiro Fujita, Indradeep Ghosh, Mukul R. Prasad: Verification Techniques for System-Level Design. The Morgan Kaufmann series in systems on silicon, Morgan Kaufmann 2008, isbn 978-0-12-370616-4, pp. I-VIII, 1-240

Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita: 3D Perception and Environment Map Generation for Humanoid Robot Navigation. I. J. Robotic Res. 27(10): 1117-1134 (2008)

Masahiro Fujita, Kenshu Seto, Thanyapat Sakunkonchak: Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation. JSAT 5(1-4): 57-82 (2008)

Hiroaki Yoshida, Masahiro Fujita: Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits. DATE 2008: 1099-1102

Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita: Multi-level Bounded Model Checking to detect bugs beyond the bound. HLDVT 2008: 49-55

Taro Takahashi, Toshimitsu Tsuboi, Takeo Kishida, Yasunori Kawanami, Satoru Shimizu, Masatsugu Iribe, Tetsuharu Fukushima, Masahiro Fujita: Adaptive grasping by multi fingered hand with tactile sensor based on robust force and position control. ICRA 2008: 264-271

Masahiro Fujita, Takeshi Matsumoto, Hiroaki Yoshida: A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams. ICSOFT (SE/MUSE/GSDCA) 2008: 240-245

Ken'ichiro Nagasaka, Atsushi Miyamoto, Masakuni Nagano, Hirokazu Shirado, Tetsuharu Fukushima, Masahiro Fujita: Motion control of a virtual humanoid that can perform real physical interactions with a human. IROS 2008: 2303-2310

O. Sarbishei, Bijan Alizadeh, Masahiro Fujita: Arithmetic Circuits Verification without Looking for Internal Equivalences. MEMOCODE 2008: 7-16

Subash Shankar, Masahiro Fujita: Rule-Based Approaches for Equivalence Checking of SpecC Programs. MEMOCODE 2008: 39-48

Kenshu Seto, Masahiro Fujita: Custom Instruction Generation with High-Level Synthesis. SASP 2008: 14-19

Shunsuke Sasaki, Tasuku Nishihara, Daisuke Ando, Masahiro Fujita: Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph. J. UCS 13(13): 1972-2001 (2007)

Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita: Protocol Transducer Synthesis using Divide and Conquer approach. ASP-DAC 2007: 280-285

Bijan Alizadeh, Masahiro Fujita: Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. ATVA 2007: 129-144

Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita: Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction. ATVA 2007: 553-563

Takeshi Matsumoto, Daisuke Ando, Tasuku Nishihara, Masahiro Fujita: Development and Verification of a Collaborative Printing Environment. C5 2007: 99-108

Bijan Alizadeh, Masahiro Fujita: A novel formal approach to generate high-level test vectors without ILP and SAT solvers. HLDVT 2007: 97-104

Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. IESS 2007: 121-134

Shunsuke Sasaki, Tasuku Nishihara, Masahiro Fujita: Slicing-based Hardware/Software Co-design Methodology From Functional Specifications. Electr. Notes Theor. Comput. Sci. 159: 265-280 (2006)

Yu Liu, Satoshi Komatsu, Masahiro Fujita: Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment. IEICE Transactions 89-A(4): 1018-1026 (2006)

Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita: Synchronization Verification in System-Level Design with ILP Solvers. IEICE Transactions 89-A(12): 3387-3396 (2006)

Yu Liu, Satoshi Komatsu, Masahiro Fujita: The AMS Extension to System Level Design Language - SpecC. IEICE Transactions 89-A(12): 3397-3407 (2006)

David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan: Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions. International Journal of Parallel Programming 34(1): 61-91 (2006)

Ken Matsui, Masahiro Fujita: Object-oriented analysis and specification for HW/SW co-design with UML diagrams. ACST 2006: 38-43

Masahiro Fujita, Tasuku Nishihara, Daisuke Ando: System LSI distributed collaborative design environment for both designers and CAD developers/engineers. C5 2006: 175-183

Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Dynamically reconfigurable protocol transducer. FPT 2006: 341-344

Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita: Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis. HLDVT 2006: 162-169

Satoshi Komatsu, Masahiro Fujita: An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme. ISCAS 2006

Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita: Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs. ISQED 2006: 370-375

Masahiro Fujita, Subash Shankar, S. Shunsuke: Equivalence checking: a rule-based approach. MEMOCODE 2006: 197

Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra: Sequential Equivalence Checking. VLSI Design 2006: 18-19

Satoshi Komatsu, Masahiro Fujita: Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications. IEICE Transactions 88-A(12): 3282-3289 (2005)

Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita: An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences. IEICE Transactions 88-A(12): 3315-3323 (2005)

Masahiro Fujita: Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. ACM Trans. Design Autom. Electr. Syst. 10(4): 610-626 (2005)

Gregory S. Hornby, Seiichi Takamura, Takashi Yamamoto, Masahiro Fujita: Autonomous evolution of dynamic gaits with two quadruped robots. IEEE Transactions on Robotics 21(3): 402-410 (2005)

Masahiro Fujita: Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. CHARME 2005: 340-344

Yosuke Bando, Takahiro Saito, Masahiro Fujita: Hexagonal storage scheme for interleaved frame buffers and textures. Graphics Hardware 2005: 33-40

Yu Liu, Satoshi Komatsu, Masahiro Fujita: AMS Extensions for Timed/Untimed System-Level Design Language. FDL 2005: 77-81

Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. FPT 2005: 137-144

Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita: System level design language extensions for timed/untimed digital-analog combined system design. ACM Great Lakes Symposium on VLSI 2005: 130-133

Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita: A modular architecture for humanoid robot navigation. Humanoids 2005: 26-31

Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita: A Floor and Obstacle Height Map for 3D Navigation of a Humanoid Robot. ICRA 2005: 1066-1071

Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita: Real-Time Path Planning for Humanoid Robot Navigation. IJCAI 2005: 1232-1237

Masahiro Fujita, Shunsuke Sasaki, Ken Matsui: Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse. IRI 2005: 318-325

Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita: Synchronization verification in system-level design with ILP solvers. MEMOCODE 2005: 121-130

Masahiro Fujita: Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL. MEMOCODE 2005: 241-242

Masahiro Fujita, Takashi Kanai: Precomputed Radiance Transfer with Spatially-Varying Lighting Effects. CGIV 2004: 101-108

Masahiro Fujita: On equivalence checking between behavioral and RTL descriptions. HLDVT 2004: 179-184

Tsutomu Sawada, Tsuyoshi Takagi, Yukiko Hoshino, Masahiro Fujita: Learning behavior selection through interaction based on emotionally grounded symbol concept. Humanoids 2004: 450-469

Yukiko Hoshino, Tsuyoshi Takagi, Ugo Di Profio, Masahiro Fujita: Behavior Description and Control using Behavior Module for Personal Robot. ICRA 2004: 4165-4171

Jens-Steffen Gutmann, Masaki Fukuchi, Masahiro Fujita: Stair climbing for humanoid robots using stereo vision. IROS 2004: 1407-1413

Tsutomu Sawada, Tsuyoshi Takagi, Masahiro Fujita: Behavior selection and motion modulation in emotionally grounded architecture for QRIO SDR-4XII. IROS 2004: 2514-2519

Fumihide Tanaka, Kuniaki Noda, Tsutomu Sawada, Masahiro Fujita: Associated Emotion and Its Expression in an Entertainment Robot QRIO. ICEC 2004: 499-504

Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita: High Level Design Validation: Current Practices and Future Directions. VLSI Design 2004: 9-11

Masahiro Fujita: Formal Verification of C Language Based VLSI Designs. VLSI Design 2004: 93-

Minoru Asada, Oliver Obst, Daniel Polani, Brett Browning, Andrea Bonarini, Masahiro Fujita, Thomas Christaller, Tomoichi Takahashi, Satoshi Tadokoro, Elizabeth Sklar, Gal A. Kaminka: An Overview of RoboCup-2002 Fukuoka/Busan. AI Magazine 24(2): 21-40 (2003)

Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika Hasegawa: An ethological and emotional basis for human-robot interaction. Robotics and Autonomous Systems 42(3-4): 191-201 (2003)

Satoshi Komatsu, Masahiro Fujita: Irredundant address bus encoding techniques based on adaptive codebooks for low power. ASP-DAC 2003: 9-14

Farzan Fallah, Indradeep Ghosh, Masahiro Fujita: Event-driven observability enhanced coverage analysis of C programs for functional validation. ASP-DAC 2003: 123-128

Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya: Logic optimization for asynchronous speed independent controllers using transduction method. ASP-DAC 2003: 197-202

Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi: Formal verification - prove it or pitch it. DAC 2003: 710-711

Edmund M. Clarke, Masahiro Fujita, David P. Gluch: Model Checking for Dependable Software-Intensive Systems. DSN 2003: 764

Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima: Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. HICSS 2003: 279

Yoshihiro Kuroki, Masahiro Fujita, Tatsuzo Ishida, Ken'ichiro Nagasaka, Jin'ichi Yamaguchi: A small biped entertainment robot exploring attractive applications. ICRA 2003: 471-476

Masahiro Fujita, Yoshihiro Kuroki, Tatsuzo Ishida, Toshi T. Doi: Autonomous behavior control architecture of entertainment humanoid robot SDR-4X. IROS 2003: 960-967

Masahiro Fujita, Kohtaro Sabe, Yoshihiro Kuroki, Tatsuzo Ishida, Toshi T. Doi: SDR-4X II: A Small Humanoid as an Entertainer in Home Environment. ISRR 2003: 355-364

Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita: Engineering Changes in Field Modifiable Architectures. MEMOCODE 2003: 87-94

Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada: Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE 2003: 41-42

Tetsuro Ogi, Toshio Yamada, Michitaka Hirose, Masahiro Fujita, Kazuto Kuzuu: High Presence Remote Presentation in the Shared Immersive Virtual World. VR 2003: 289-290

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita: Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods in System Design 21(1): 95-101 (2002)

Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum: Program slicing for VHDL. STTT 4(1): 125-137 (2002)

Thanyapat Sakunkonchak, Masahiro Fujita: Verification of Event-Based Synchronization of SpecC Description Using Difference Decision Diagrams. FORTE 2002: 369

Masao Kubo, Masahiro Fujita: Debug methodology for arithmetic circuits on FPGAs. FPT 2002: 236-242

Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita: Field modifiable architecture with FPGAs and its design methodology. FPT 2002: 382-385

Hiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak, Masahiro Fujita, Takashi Nanya: An equivalence checking methodology for hardware oriented C-based specifications. HLDVT 2002: 139-144

Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita: Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS 2002: 103-108

Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya: Logic Optimization for Asynchronous SI Controllers using Transduction Method. IWLS 2002: 245-250

Hiroshi Nakamura, Takanori Arai, Masahiro Fujita: Formal Verification of a Pipelined Processor with New Memory. PRDC 2002: 321-324

Masahiro Fujita: Sony Four Legged Robot League at RoboCup 2002. RoboCup 2002: 469-476

Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita: Simultaneous Circuit Transformation and Routing. VLSI Design 2002: 479-483

Masahiro Fujita: AIBO: Toward the Era of Digital Creatures. I. J. Robotic Res. 20(10): 781-794 (2001)

Jawahar Jain, Ingo Wegener, Masahiro Fujita: A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. IEEE Trans. Computers 50(11): 1289-1290 (2001)

Indradeep Ghosh, Masahiro Fujita: Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 402-415 (2001)

Masahiro Fujita, Gabriel Costa, Rika Hasegawa, Tsuyoshi Takagi, Jun Yokono, Hideki Shimomura: Architecture and preliminary experimental results for emotionally grounded symbol acquisition. Agents 2001: 35-36

Ronald C. Arkin, Masahiro Fujita, Tsuyoshi Takagi, Rika Hasegawa: Ethological Modeling and Architecture for an Entertainment Robot. ICRA 2001: 453-458

Masahiro Fujita, Hiroshi Nakamura: The standard SpecC language. ISSS 2001: 81-86

Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda: New design paradigms. ISSS 2001: 94

Takashi Michikawa, Takashi Kanai, Masahiro Fujita, Hiroaki Chiyokura: Multiresolution Interpolation Meshes. Pacific Conference on Computer Graphics and Applications 2001: 60-69

Masahiro Fujita, Manuela M. Veloso, William T. B. Uther, Minoru Asada, Hiroaki Kitano, Vincent Hugel, Patrick Bonnin, Jean-Christophe Bouramoué, Pierre Blazevic: Vision, Strategy, and Localization Using the Sony Robots at RoboCup-98. AI Magazine 21(1): 47-56 (2000)

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita: Automatic partitioning for efficient combinatorial verification. ASP-DAC 2000: 67-72

Indradeep Ghosh, Masahiro Fujita: Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. DAC 2000: 43-48

Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita: Efficient variable ordering using aBDD based sampling. DAC 2000: 687-692

Gregory Hornby, Seiichi Takamura, Osamu Hanagata, Masahiro Fujita, Jordan B. Pollack: Evolution of Controllers from a High-Level Simulator to a High DOF Robot. ICES 2000: 80-89

Masahiro Fujita: Digital Creatures for Future Entertainment Robotics. ICRA 2000: 801-806

Gregory Hornby, Seiichi Takamura, Jun Yokono, Osamu Hanagata, Takashi Yamamoto, Masahiro Fujita: Evolving Robust Gaits with AIBO. ICRA 2000: 3040-3045

Minoru Asada, Andreas Birk, Enrico Pagello, Masahiro Fujita, Itsuki Noda, Satoshi Tadokoro, Dominique Duhaut, Peter Stone, Manuela M. Veloso, Tucker R. Balch, Hiroaki Kitano, Brian Thomas: Progress in RoboCup Soccer Research in 2000. ISER 2000: 363-372

Peter Stone, Minoru Asada, Tucker R. Balch, Masahiro Fujita, Gerhard K. Kraetzschmar, Henrik Hautop Lund, Paul Scerri, Satoshi Tadokoro, Gordon Wyeth: Overview of RoboCup-2000. RoboCup 2000: 1-28

Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita: Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design 2000: 436-441

Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao: Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS 2000: 263-270

Ashok Sudarsanam, Sharad Malik, Masahiro Fujita: A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library. Design Autom. for Emb. Sys. 4(2-3): 187-206 (1999)

Masahiro Fujita, Hiroaki Kitano, Koji Kageyama: A reconfigurable robot platform. Robotics and Autonomous Systems 29(2-3): 119-132 (1999)

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: An efficient filter-based approach for combinational verification. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1542-1557 (1999)

Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita: Model Checking Based on Sequential ATPG. CAV 1999: 418-430

Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum: Program Slicing of Hardware Description Languages. CHARME 1999: 298-312

Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik: Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. CODES 1999: 2-6

Armin Biere, Alessandro Cimatti, Edmund M. Clarke, Masahiro Fujita, Yunshan Zhu: Symbolic Model Checking Using SAT Procedures instead of BDDs. DAC 1999: 317-320

Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni: Multiple Error Diagnosis Based on Xlists. DAC 1999: 660-665

Rajeev Murgai, Masahiro Fujita: On Reducing Transitions Through Data Modifications. DATE 1999: 82-

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: An Efficient Filter-Based Approach for Combinational Verification. DATE 1999: 132-137

Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita: Speeding Up Look-up-Table Driven Logic Simulation. VLSI 1999: 385-397

Manuela M. Veloso, Hiroaki Kitano, Enrico Pagello, Gerhard K. Kraetzschmar, Peter Stone, Tucker R. Balch, Minoru Asada, Silvia Coradeschi, Lars Karlsson, Masahiro Fujita: Overview of RoboCup-99. RoboCup 1999: 1-34

Rajeev Murgai, Jawahar Jain, Masahiro Fujita: Efficient Scheduling Techniques for ROBDD Construction. VLSI Design 1999: 394-401

Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita: On the Evaluation of Arbitrary Defect Coverage of Test Sets. VTS 1999: 426-432

Masahiro Fujita, Hiroaki Kitano: Development of an Autonomous Quadruped Robot for Robot Entertainment. Auton. Robots 5(1): 7-18 (1998)

Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee: ATM switch design by high-level modeling, formal verification and high-level synthesi. ACM Trans. Design Autom. Electr. Syst. 3(4): 554-562 (1998)

Masahiro Fujita, Hiroaki Kitano, Koji Kageyama: Reconfigurable Physical Agents. Agents 1998: 54-61

Juan D. Velásquez, Masahiro Fujita, Hiroaki Kitano: An Open Architecture of Remotion and Behavior Control of Autonomous Agents. Agents 1998: 473-474

Masahiro Fujita: Model Checking: Its Basics and Reality (Embedded Tutorial). ASP-DAC 1998: 217-222

Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira: Using Complementation and Resequencing to Minimize Transitions. DAC 1998: 694-697

Masahiro Fujita, Sreeranga P. Rajan, Alan J. Hu: Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol. FM-Trends 1998: 281-295

Jawahar Jain, William Adams, Masahiro Fujita: Sampling schemes for computing OBDD variable orderings. ICCAD 1998: 631-638

Hiroaki Kitano, Masahiro Fujita, Stéphane Zrehen, Koji Kageyama: Sony Legged Robot for RoboCup Challenge. ICRA 1998: 2605-2612

Vamsi Boppana, Masahiro Fujita: Modeling the unknown! Towards model-independent fault and error diagnosis. ITC 1998: 1094-1101

Masahiro Fujita, Stéphane Zrehen, Hiroaki Kitano: A Quadruped Robot for RoboCup Legged Robot Challenge in Paris '98. RoboCup 1998: 125-140

Sreeranga P. Rajan, Masahiro Fujita: Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. VLSI Design 1998: 552-557

Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita: Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping. Design Autom. for Emb. Sys. 2(3-4): 319-338 (1997)

Masahiro Fujita, Patrick C. McGeer: Introduction to the Special Issue on Multi-Terminal Binary Decision Diagrams. Formal Methods in System Design 10(2/3): 135-136 (1997)

Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, J. Yang: Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. Formal Methods in System Design 10(2/3): 137-148 (1997)

Masahiro Fujita, Patrick C. McGeer, Jerry Chih-Yuan Yang: Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation. Formal Methods in System Design 10(2/3): 149-169 (1997)

Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita: Power analysis and minimization techniques for embedded DSP software. IEEE Trans. VLSI Syst. 5(1): 123-135 (1997)

Masahiro Fujita, Koji Kageyama: An Open Architecture for Robot Entertainment. Agents 1997: 435-442

Sreeranga P. Rajan, Masahiro Fujita: ATM Switch Design: Parametric High-Level Modeling and Formal Verification. AMAST 1997: 437-450

Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita: Speeding up technology-independent timing optimization by network partitioning. ICCAD 1997: 83-90

Alan J. Hu, Masahiro Fujita, Chris Wilson: Formal Verification of the HAL S1 System Cache Coherence Protocol. ICCD 1997: 438-444

Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli: A Survey of Techniques for Formal Verification of Combinational Circuits. ICCD 1997: 445-454

Masahiro Fujita, Hiroaki Kitano, Koji Kageyama: A Legged Robot for RoboCup Based on "OPENR". RoboCup 1997: 168-180

Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli: Formal Verification of Combinational Circuit. VLSI Design 1997: 218-225

Rajeev Murgai, Masahiro Fujita: Some Recent Advances in Software and Hardware Logic Simulation. VLSI Design 1997: 232-238

Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi: Solving the net matching problem in high-performance chip design. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 902-911 (1996)

Masahiro Fujita: Verification of Arithmetic Circuits by Comparing Two Similar Circuits. CAV 1996: 159-168

Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita: Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. DAC 1996: 585-590

Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita: Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434

Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli: Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. ICCAD 1996: 547-554

Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: On More Efficient Combinational ATPG Using Functional Learning. VLSI Design 1996: 107-110

Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253

Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita: Advanced Verification Techniques Based on Learning. DAC 1995: 420-426

Edmund M. Clarke, Masahiro Fujita, Xudong Zhao: Hybrid decision diagrams. ICCAD 1995: 159-163

Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose: Logic synthesis for a single large look-up table. ICCD 1995: 415-

Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng: Simple tree-construction heuristics for the fanout problem . ICCD 1995: 671-679

Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita: Power analysis and low-power scheduling techniques for embedded DSP software. ISSS 1995: 110-115

Ben Chen, Michihiro Yamazaki, Masahiro Fujita: Bug Identification of a Real Chip Design by Symbolic Model Checking. EDAC-ETC-EUROASIC 1994: 132-136

Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita: LP based cell selection with constraints of timing, area, and power consumption. ICCAD 1994: 378-381

Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton: A redesign technique for combinational circuits based on gate reconnections. ICCAD 1994: 632-637

H. Sato, Michihiro Yamazaki, Masahiro Fujita: YEPHCAD and FLORA: Logic Synthesis for Control and Datapath. ICCD 1994: 527-530

Masahiro Fujita, Jerry Chih-Yuan Yang, Edmund M. Clarke, Xudong Zhao, Patrick C. McGeer: Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams. ISCAS 1994: 275-278

Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga: Variable ordering algorithms for ordered binary decision diagrams and their evaluation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 6-12 (1993)

Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, J. Yang: Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. DAC 1993: 54-60

Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita: An efficient algorithm for the net matching problem. ICCAD 1993: 640-644

Masahiro Fujita, Shinji Kono: Synthesis of Controllers from Interval Temporal Logic Specification. ICCD 1993: 242-245

T. Sakaguchi, Masahiro Fujita, Hiroshi Watanabe, Fumio Miyazaki: Motion Planning and Control for a Robot Performer. ICRA (3) 1993: 925-931

Kuang-Chien Chen, Masahiro Fujita: Efficient Sum-to-One Subsets Algorithm for Logic Optimization. DAC 1992: 443-448

Masahiro Fujita, Yuji Kukimoto: Patching Method for Lookup-Table Type FPLs. FPL 1992: 61-70

Yuji Kukimoto, Masahiro Fujita: Rectification method for lookup-table type FPGA's. ICCAD 1992: 54-61

Masahiro Fujita: RTL Design Verification by Making Use of Datapath Information. ICCD 1992: 592-597

Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita: A Resynthesis Approach for Network Optimization. DAC 1991: 458-463

Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen: Application of Boolean Unification to Combinational Logic Synthesis. ICCAD 1991: 510-513

Masahiro Fujita, Yusuke Matsunaga: Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. ICCAD 1991: 560-563

Kuang-Chien Chen, Masahiro Fujita: Concurrent Resynthesis for Network Optimization. ICCD 1991: 44-48

Zhen-Ping Lo, Masahiro Fujita, Behnam Bavarian: Analysis of Neighborhood Interaction in Kohonen Neural Networks. IPPS 1991: 246-249

Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka: A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV 1990: 76-85

Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita: Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. DAC 1990: 284-289

Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda: Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. ICCAD 1990: 38-41

Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda: Multi-Level Logic Minimization Across Latch Boundaries. ICCAD 1990: 406-409

Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita, Hidehiko Tanaka: Logic Design Assistence Using Temporal Logic Based Language Tokio. LP 1989: 174-183

Masahiro Fujita, Shinji Kono, Hidehiko Tanaka, Tohru Moto-Oka: Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog. ICLP 1986: 695-709

T. Aoyagi, Masahiro Fujita, Tohru Moto-Oka: Temporal Logic Programming Language Tokio - Programming in Tokio. LP 1985: 128-137

Shinji Kono, T. Aoyagi, Masahiro Fujita, Hidehiko Tanaka: Implementation of Temporal Logic Programming Language Tokio. LP 1985: 138-147

Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko Tanaka, Tohru Moto-Oka: Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis. LP 1985: 246-255

Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka: Specifying Hardware in temporal Logic & Efficient Synthesis of State-Diagrams Using Prolog. FGCS 1984: 572-581

Masahiro Fujita, Hidehiko Tanaka, Tohru Moto-Oka: Temporal Logic Based Hardware Description and Its Verification with Prolog. New Generation Comput. 1(2): 195-203 (1983)