ISQED 2010: San Jose, California, USA

• Kamesh V. Gadepally, Lalitha Immaneni, Pallab Chatterjee, George Alexiou, Ali Iranmanesh:
  Welcome to ISQED 2010.
  
• Leon O. Chua:
  ISQED quality award recipient (IQ-Award 2010).
  
• Daniela De Venuto:
  ISQED 2010 fellow award recipient.
  

SRAM Manufacturability

• Randy W. Mann, Satyanand Nalam, Jiajing Wang, Benton H. Calhoun:
  Limits of bias based assist methods in nano-scale 6T SRAM. 1-8
  
• Touqeer Azam, Binjie Cheng, David R. S. Cumming:
  Variability resilient low-power 7T-SRAM design for nano-scaled technologies. 9-14
  
• Takanori Date, Shiho Hagiwara, Kazuya Masu, Takashi Sato:
  Robust importance sampling for efficient SRAM yield analysis. 15-21
  
• Hidetoshi Matsuoka, Hiroshi Ikeda, Hiroyuki Higuchi, Yoshinori Tomita:
  An accurate modeling method utilizing application-specific statistical information and its application to SRAM yield estimation. 22-28
  

Mixed Signal and Power Control Circuits

• Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
  Adaptive power gating for function units in a microprocessor. 29-37
  
• Kyu-Nam Shim, Jiang Hu, José Silva-Martínez:
  A dual-level adaptive supply voltage system for variation resilience. 38-43
  
• Mallik Kandala, Ramgopal Sekar, Chenglong Zhang, Haibo Wang:
  A low power charge-redistribution ADC with reduced capacitor array. 44-48
  
• Ankit More, Baris Taskin:
  Leakage current analysis for intra-chip wireless interconnects. 49-53
  

Guaranteeing Timing Performance

• Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang:
  Toward effective utilization of timing exceptions in design optimization. 54-61
  
• Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu:
  Useful clock skew optimization under a multi-corner multi-mode design framework. 62-68
  
• Minseok Kang, Taewhan Kim:
  Clock buffer polarity assignment considering the effect of delay variations. 69-74
  
• Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato:
  Linear time calculation of state-dependent power distribution network capacitance. 75-80
  

Analog Design For Reliability

• Venkata Naresh Mudhireddy, Saravanan Ramamoorthy, Haibo Wang:
  Implementing self-testing and self-repairable analog circuits on field programmable analog array platforms. 81-86
  
• Ming-Ta Yang, Yang Du, Charles Teng, Tony Chang, Eugene Worley, Ken Liao, You-Wen Yau, Geoffrey Yeap:
  BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit. 87-91
  
• Yang Liu, Ashok Srivastava:
  Hot carrier effects on CMOS phase-locked loop frequency synthesizers. 92-98
  
• Jun Zhao, Yong-Bin Kim:
  A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur. 99-102
  

Lithography & Manufacturing

• Peter Buck, Franklin Kalk, Craig West:
  Photomasks and the enablement of circuit design complexity. 103-107
  
• Yao Peng, Jinyu Zhang, Yan Wang, Zhiping Yu:
  High performance source optimization using a gradient-based method in optical lithography. 108-113
  
• Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costas J. Spanos:
  Yield-constrained digital circuit sizing via sequential geometric programming. 114-121
  
• Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu:
  Assessing chip-level impact of double patterning lithography. 122-130
  

Power Aware Memory Design

• Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan:
  A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. 131-138
  
• Satyanand Nalam, Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken, Benton H. Calhoun:
  Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation. 139-146
  
• Srikanth V. Devarapalli, Payman Zarkesh-Ha, Steven C. Suddarth:
  A robust and low power dual data rate (DDR) flip-flop using c-elements. 147-150
  
• Jun Xu, Ge Zhang, Weiwu Hu:
  Optimizing power and throughput for m-out-of-n encoded asynchronous circuits. 151-157
  

Poster Session 1

• Vivek Joshi, Kanak Agarwal, Dennis Sylvester:
  Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices. 158-162
  
• Vivek S. Nandakumar, David Newmark, Yaping Zhan, Malgorzata Marek-Sadowska:
  Statistical static timing analysis flow for transistor level macros in a microprocessor. 163-170
  
• Patrick Gibson, Ziyang Lu, Fedor Pikus, Sridhar Srinivasan:
  A framework for logic-aware layout analysis. 171-175
  
• Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan:
  P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP. 176-183
  
• Masanori Kurimoto, Jun Matsushima, Shigeki Ohbayashi, Yoshiaki Fukui:
  A yield improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push rule. 184-190
  
• Bingbing Xia, Fei Qiao, Huazhong Yang, Hui Wang:
  A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design. 191-197
  
• Izumi Nitta, Yuji Kanazawa, Daisuke Fukuda, Toshiyuki Shibuya, Naoki Idani, Masaru Ito, Osamu Yamasaki, Norihiro Harada, Takanori Hiramoto:
  "Condition-based" dummy fill insertion method based on ECP and CMP predictive models. 198-205
  
• Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, Young-Sang Son, Dae-Woo Kim:
  Analysis and modeling of a Low Voltage Triggered SCR ESD protection clamp with the very fast Transmission Line Pulse measurement. 206-210
  
• Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan:
  On the design of different concurrent EDC schemes for S-Box and GF(p). 211-218
  
• Kyung Ki Kim, Haiqing Nan, Ken Choi:
  Adaptive HCI-aware power gating structure. 219-224
  
• Fan Wang, Vishwani D. Agrawal:
  Soft error rate determination for nanoscale sequential logic. 225-230
  
• Farzan Rezaei, Seyed Javad Azhari:
  Ultra low-voltage, rail-to-rail input/output stage Operational Transconductance Amplifier (OTA) with high linearity and its application in a Gm-C filter. 231-236
  
• Chia-Yi Lin, Hung-Ming Chen:
  A novel two-dimensional scan-control scheme for test-cost reduction. 237-243
  
• Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aamodt:
  Accelerating trace computation in post-silicon debug. 244-249
  
• Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman:
  Structural fault collapsing by superposition of BDDs for test generation in digital circuits. 250-257
  
• Sreenivas Gangadhar, Spyros Tragoudas:
  A novel probabilistic SET propagation method. 258-263
  
• Kusum Lata, H. S. Jamadagni:
  Formal verification of Full-Wave Rectifier using SPICE circuit simulation traces. 264-270
  
• Pablo A. Petrashin, Gabriela Peretti, Eduardo Romero:
  OBT implementation on an OTA-C band-pass filter. 271-276
  
• Yu Zhong, Martin D. F. Wong:
  Fast block-iterative domain decomposition algorithm for IR drop analysis in large power grid. 277-283
  
• Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang:
  A non-parametric approach to behavioral device modeling. 284-290
  

Variability: Design, Test, and Characterization

• Jin Sun, Janet Meiling Wang:
  Robust gate sizing by Uncertainty Second Order Cone. 291-298
  
• Chris Allsup:
  Is built-in logic redundancy ready for prime time? 299-306
  
• John Sartori, Aashish Pant, Rakesh Kumar, Puneet Gupta:
  Variation-aware speed binning of multi-core processors. 307-314
  
• Jeanne Bickford, Nazmul Habib, John Goss, Robert McMahon, Rajiv V. Joshi, Rouwaida Kanj:
  Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test. 315-319
  
• Ender Yilmaz:
  Accurate multi-specification DPPM estimation using layered sampling based simulation. 320-326
  

Emerging Device and Design Technniques

• Yiran Chen, Wei Tian, Hai Li, Xiaobin Wang, Wenzhong Zhu:
  Scalability of PCMO-based resistive switch device in DSM technologies. 327-332
  
• Jeremy R. Tolbert, Pratik Kabali, Simeranjit Brar, Saibal Mukhopadhyay:
  A low power system with adaptive data compression for wireless monitoring of physiological signals and its application to wireless electroencephalography. 333-341
  
• Saeroonter Oh, Jeongha Park, S. Simon Wong, H.-S. Philip Wong:
  Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design. 342-346
  
• Prateek Mishra, Ajay N. Bhoj, Niraj K. Jha:
  Die-level leakage power analysis of FinFET circuits considering process variations. 347-355
  
• Wei Xu, Tong Zhang:
  Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory. 356-361
  

Power and Performance Issues in System-Level Design

• Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram:
  Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint. 362-371
  
• Yang Liu, Jibang Liu, Tong Zhang:
  Design of low-power variation tolerant signal processing systems with adaptive finite word-length configuration. 372-379
  
• Lech Józwiak, Yahya Jan:
  Quality-driven methodology for demanding accelerator design. 380-389
  
• Shaobo Liu, Jingyi Zhang, Qing Wu, Qinru Qiu:
  Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor. 390-398
  
• Shengquan Wang, Jian-Jia Chen:
  Thermal-aware lifetime reliability in multicore systems. 399-405
  

Poster Session 2

• Mingzhi Gao, Zuochang Ye, Yao Peng, Yan Wang, Zhiping Yu:
  A comprehensive model for gate delay under process variation and different driving and loading conditions. 406-412
  
• Vinayak Honkote, Baris Taskin:
  Skew analysis and bounded skew constraint methodology for rotary clocking technology. 413-417
  
• Kanad Chakraborty:
  A MATLAB-based technique for defect level estimation using data mining of test fallout data versus fault coverage. 418-421
  
• Long Fei, Loa Mize, Cho Moon, Bill Mullen, Sonia Singhal:
  Constraint analysis and debugging for multi-million instance SoC designs. 422-427
  
• Vee Kin Wong, Siong Kiong Teng:
  Variation aware guard -banding for SOC static timing analysis. 428-431
  
• Chenyue Ma, Hao Wang, Xiufang Zhang, Frank He, Yadong He, Xing Zhang, Xinnan Lin:
  Asymmetric issues of FinFET device after hot carrier injection and impact on digital and analog circuits. 432-436
  
• Khalil Monfaredi, Hassan Faraji Baghtash, Seyed Javad Azhari:
  A novel low voltage current compensated high performance current mirror/NIC. 437-442
  
• Jinhui Wang, Wuchen Wu, Na Gong, Ligang Hou:
  Domino gate with modified voltage keeper. 443-446
  
• Huang Huang, Gang Quan, Jeffrey Fan:
  Leakage temperature dependency modeling in system level analysis. 447-452
  
• Ethiopia Nigussie, Juha Plosila, Jouni Isoaho:
  Process variation tolerant on-chip communication using receiver and driver reconfiguration. 453-460
  
• Basab Datta, Wayne P. Burleson:
  Calibration of on-chip thermal sensors using process monitoring circuits. 461-467
  
• Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yngvar Berg, Tuan Vu Cao:
  New SRAM design using body bias technique for ultra low power applications. 468-471
  
• Maurice Meijer, José Pineda de Gyvez:
  Body bias driven design synthesis for optimum performance per area. 472-477
  
• Nitin Srimal:
  Methodology to ensure circuit robustness and exceptional silicon quality while proliferating designs across process revisions with high productivity. 478-482
  
• Yu Cheng Hu, Yin Lin Chung, Mely Chen Chi:
  A multilevel multilayer partitioning algorithm for three dimensional integrated circuits. 483-487
  
• Siong Kiong Teng, Norhayati Soin:
  Low power clock gates optimization for clock tree distribution. 488-492
  
• John Ferguson, Sandeep Koranne, David Abercrombie:
  An innovative method to automate the waiver of IP-level DRC violations. 493-498
  
• Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi:
  Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. 499-507
  
• Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee:
  Antenna Violation Avoidance/Fixing for X-clock routing. 508-514
  
• Masahiro Fujita, Hideo Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto:
  Synthesis and formal verification of on-chip protocol transducers through decomposed specification. 515-523
  
• Hicham Ezzat, Lirida A. B. Naviner:
  Level matrix propagation for reliability analysis of nano-scale circuits based on probabilistic transfer matrix. 524-527
  
• Abishek Mann, Amit Karalkar, Lili He, Morris Jones:
  The design of a low-power low-noise phase lock loop. 528-531
  
• Daniela De Venuto, Eduard Stikvoort, David Tio Castro, Youri Ponomarev:
  Novel low-power 12-bit SAR ADC for RFID tags. 532-537
  
• Tongquan Wei, Yonghe Guo, Xiaodao Chen, Shiyan Hu:
  Adaptive task allocation for multiprocessor SoCs. 538-543
  
• Suraya Bt Mohd Yusof, Lau Meng Tee:
  Multi-programming environment for structure under pads (SUP) and via arrays pattern recognition automated classification system. 544-561
  

Parametric and Delay Test

• Sachin Dileep Dasnurkar, Jacob A. Abraham:
  Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM. 562-569
  
• Jing Zeng, Jing Wang, Chia-Ying Chen, Michael Mateja, Li-C. Wang:
  On evaluating speed path detection of structural tests. 570-576
  
• Manu Baby, Vijay Sarathi:
  Slack-based approach for peak power reduction during transition fault testing. 577-581
  
• Ramyanshu Datta, Mahit Warhadpande, Dale Heaton, S. Aarthi, Ram Jonnavithula:
  Case studies of mixed-signal DFT. 582-589
  

PDI

• Mosin Mondal, James Pingenot, Vikram Jandhyala:
  Efficient hierarchical discretization of off-chip power delivery network geometries for 2.5D electrical analysis. 590-597
  
• Rajeev K. Nain, Shantesh Pinge, Malgorzata Chrzanowska-Jeske:
  Yield improvement of 3D ICs in the presence of defects in through signal vias. 598-605
  

Advances in Power Distribution, Placement and Routing

• Qiang Ma, Tan Yan, Martin D. F. Wong:
  A negotiated congestion based router for simultaneous escape routing. 606-610
  
• S. K. Nithin, Gowrysankar Shanmugam, Sreeram Chandrasekar:
  Dynamic voltage (IR) drop analysis and design closure: Issues and challenges. 611-617
  
• Yu-Ming Yang, Iris Hui-Ru Jiang:
  Analog placement and global routing considering wiring symmetry. 618-623
  
• Peng Du, Xiang Hu, Shih-Hung Weng, Amirali Shayan Arani, Xiaoming Chen, A. Ege Engin, Chung-Kuan Cheng:
  Worst-case noise prediction with non-zero current transition times for early power distribution system verification. 624-631
  
• Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto:
  Fixed outline multi-bend bus driven floorplanning. 632-637
  

Aging Analysis & Mitigation

• Jianxin Fang, Sachin S. Sapatnekar:
  Scalable methods for the analysis and optimization of gate oxide breakdown. 638-645
  
• Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
  Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. 646-651
  
• Hamed Abrishami, Safar Hatami, Massoud Pedram:
  Multi-corner, energy-delay optimized, NBTI-aware flip-flop design. 652-659
  
• Yuji Kunitake, Toshinori Sato, Hiroto Yasuura:
  Signal probability control for relieving NBTI in SRAM cells. 660-666
  
• Göran Jerke, Jens Lienig:
  Early-stage determination of current-density criticality in interconnects. 667-674
  

Test, Quality, Cost and Debug

• Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour:
  Automated silicon debug data analysis techniques for a hardware data acquisition environment. 675-682
  
• Savita Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
  Layout-aware Illinois Scan design for high fault coverage coverage. 683-688
  
• Abdallatif S. Abu-Issa, Steven F. Quigley:
  Multi-degree smoother for low power consumption in single and multiple scan-chains BIST. 689-696
  
• Sandesh Prabhakar, Michael S. Hsiao:
  Multiplexed trace signal selection using non-trivial implication-based correlation. 697-704
  
• Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronald Syzdek:
  Modeling and verification of industrial flash memories. 705-712
  

System-level NoC, SoC and ASIC design

• Angada B. Sachid, Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao, Mahesh B. Patil:
  Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework. 713-720
  
• Shirish Bahirat, Sudeep Pasricha:
  UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications. 721-729
  
• Alexandra Aguiar, Sergio Johann Filho, Felipe G. Magalhaes, Thiago D. Casagrande, Fabiano Hessel:
  Hellfire: A design framework for critical embedded systems' applications. 730-737
  
• Brett H. Meyer, Adam S. Hartman, Donald E. Thomas:
  Slack allocation for yield improvement in NoC-based MPSoCs. 738-746
  
• Mahmoud Momtazpour, Esmaeil Sanaei, Maziar Goudarzi:
  Power-yield optimization in MPSoC task scheduling under process variation. 747-754
  

Clocking Strategy for Modern Low Power Multi-Core & Structured ASICs

• Min Ni, Seda Ogrenci Memik:
  A revisit to the primal-dual based clock skew scheduling algorithm. 755-764
  
• Jianchao Lu, Baris Taskin:
  Clock buffer polarity assignment considering capacitive load. 765-770
  
• Dawei Liu, Qiang Zhou, Yongqiang Lu, Jinian Bian:
  A low power clock network placement framework. 771-776
  
• Rung-Bin Lin, I-Wei Lee, Wen-Hao Chen:
  Clock routing for structured ASICs with via-configurable fabrics. 777-784
  
• Derek Chan, Matthew R. Guthaus:
  Analysis of power supply induced jitter in actively de-skewed multi-core systems. 785-790
  

Modeling and Analysis of Temperature and Power

• Abhishek A. Sinkar, Nam Sung Kim:
  Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits. 791-796
  
• Minki Cho, Saibal Mukhopadhyay:
  Signal processing methods and hardware-structure for on-line characterization of thermal gradients in many-core processors. 797-803
  
• Sanghamitra Roy, Koushik Chakraborty:
  A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures. 804-811
  
• Eun Ju Hwang, Wook Kim, Young Hwan Kim:
  Improving the process variation tolerability of flip-flops for UDSM circuit design. 812-817
  
• Jun-Kuei Zeng, Chung-Ping Chen:
  Interconnect delay and slew metrics using the extreme value distribution. 818-823
  

Fault Tolerant Design

• Yongpan Liu, Yinan Sun, Yihao Zhu, Huazhong Yang:
  Design methodology of variable latency adders with multistage function speculation. 824-830
  
• Yu-Hsin Kuo, Huan-Kai Peng, Charles H.-P. Wen:
  Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models. 831-838
  
• Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
  Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. 839-844
  
• Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
  Design of a fault-tolerant coarse-grained. 845-852
  
• David Li, Pierce Chuang, Manoj Sachdev:
  Comparative analysis and study of metastability on high-performance flip-flops. 853-860
  

Quality System-Level Design

• Xin Pan, Helmut Graeb:
  Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rate. 861-865
  
• Dongkeun Oh, Charlie Chung-Ping Chen, Nam Sung Kim, Yu Hen Hu:
  The compatibility analysis of thread migration and DVFS in multi-core processor. 866-871
  
• Hui Li, Makram Mansour, Sury Maturi, Li-C. Wang:
  Analog behavioral modeling flow using statistical learning method. 872-878
  
• Avinash Lakshminarayana, Sumit Ahuja, Sandeep K. Shukla:
  Coprocessor design space exploration using high level synthesis. 879-884
  
• Kwangok Jeong, Andrew B. Kahng:
  Methodology from chaos in IC implementation. 885-892
  

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