Proceedings of the International Conference on Parallel Processing, ICPP '89, The Pennsylvania State University, University Park, PA, USA, August 1989. ISBN 0-271-00686-2, Vol.1: Architecture

Hot Spots

• 
  Nian-Feng Tzeng: Design of a Novel Combining Structure for Shared-Memory Multiprocessors. 1-8
• 
  Daniel M. Dias, Manoj Kumar: Preventing Congestion in Multistage Networks in the Presence of Hotspots. 9-13
• 
  Wing S. Ho, Derek L. Eager: A Novel Strategy for Controlling Hot Spot Congestion. 14-18
• 
  Lance Kurisaki, Tomás Lang: Multistage Networks Including Traffic with Real-Time Constraints. 19-22

Caches

• 
  Sang Lyul Min, Jean-Loup Baer: A Timestamp-based Cache Coherence Scheme. 23-32
• 
  Craig B. Stunkel, W. Kent Fuchs: Analysis of Hypercube Cache Performance Using Address Traces Generated by TRAPEDS. 33-40
• 
  Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan: Extending the Memory Hierarchy into Multiprocessor Interconnection Networks: A Performance Analysis. 41-50
• 
  Laxmi N. Bhuyan, Bao-Chyn Liu, Irshad Ahmed: Analysis of MIN Based Multiprocessors with Private Cache Memories. 51-58

Analysis Techniques

• 
  Edward C. Bronson, Thomas L. Casavant, Leah H. Jamieson: Experimental Application-Driven Architecture Analysis of an SIMD/MIMD Parallel Processing System. 59-67
• 
  Manoj Kumar, Kimming So: Trace Driven Simulation for Studying MIMD Parallel Computers. 68-72
• 
  Laxmi N. Bhuyan, Hong Jiang, Dipak Ghosal: From Interconnection Network To Task Level Analysis. 73-77
• 
  Sandra Johnson Baylor, Bharat Deep Rathi: A Study of the Memory Reference Behavior of Engineering/Scientific Applications in Parallel Processors. 78-82

Databases

• 
  M. Seetha Lakshmi, Philip S. Yu: Analysis of Parallel Processing Architectures for Database Systems. 83-90
• 
  Myoung-Ho Kim, Sakti Pramanik: On the Data Distribution Problems for Range Queries. 91-94
• 
  Zhenqiang Fan, Kam-Hoi Cheng: A Simultaneous Access Priority Queue. 95-98
• 
  Constantinos T. Davarakis, Dimitris G. Maritsas: A Parallel Associative Query Set of Algorithms (PASQ-set) and the MULTI-layer Associative Processor Model. 99-102

Networks I

• 
  Ted H. Szymanski: On the Permutation Capability of a Circuit-Switched Hypercube. 103-110
• 
  Philip J. Bernhard, Harry B. Hunt III, Daniel J. Rosenkrantz: Compaction of Message Patterns into Space-Efficient Representations for Multiprocessor Interconnection Networks. 111-115
• 
  Seth Abraham, Krishnan Padmanabhan: An Analysis of the Twisted Cube Topology. 116-120
• 
  Oscar H. Ibarra, Stephen M. Sohn: On Mapping Systolic Algorithms onto the Hypercube. 121-124

Virtual Shared-Memory

• 
  Kai Li, Richard Schaefer: A Hypercube Shared Virtual Memory System. 125-132
• 
  Roberto Bisiani, Andreas Nowatzyk, Mosur Ravishankar: Coherent Shared Memory on a Distributed Memory Machine. 133-141
• 
  Larry D. Wittie, Creve Maples: MERLIN: Massively Parallel Heterogeneous Computing. 142-150
• 
  Lothar Borrmann, Martin Herdieckerhoff: Parallel Processing Performance in a Linda System. 151-158

Faults and Failures

• 
  Kun-Lung Wu, W. Kent Fuchs, Janak H. Patel: Cache-Based Error Recovery for Shared Memory Multiprocessor Systems. 159-166
• 
  Phillip F. Chimento Jr., Kishor S. Trivedi: Completion Times of Programs on Concurrent Processors with Failure and Repair. 167-171
• 
  Tsang-Ling Sheu, Woei Lin, Chita R. Das, Mary Jane Irwin: Distributed Fault Diagnosis in the Butterfly Parallel Processor. 172-175
• 
  Arif Ghafoor, Sohail Sheikh, Patrick Solé: Distance-Transitive Graphs for Fault-Tolerant Multiprocessor Systems. 176-179

Networks II

• 
  Shahram Latifi, Ahmed El-Amawy: On Folded Hypercubes. 180-187
• 
  Piotr Berman, Juan A. Garay: Efficient Agreement on Bounded-Degree Networks. 188-191
• 
  Chungti Liang, Yigang Chen, Wei-Tek Tsai: Embedding of Linear Array and Binary Tree in Cubical Ring Connected Cycles Networks. 192-195
• 
  Gregory T. Byrd, Nakul P. Saraiya, Bruce Delagi: Multicast Communication in Multiprocessor Systems. 196-200

Data-Driven Architectures

• 
  A. P. Wim Böhm, John R. Gurd, Yong Meng Teo: The Effect of Iterative Instructions in Dataflow Computers. 201-208
• 
  Keshab K. Parhi, David G. Messerschmitt: Fully-Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding. 209-216
• 
  Tetsuya Higuchi, Tatsumi Furuya, Hiroyuki Kusumoto, Ken'ichi Handa, Akio Kokubu: The Prototype of a Semantic Network Machine IXM. 217-224

Memory Interference

• 
  Badie A. Taha, Hilda M. Standley: A General Model for Memory Interference in a Multiprocessor System with Memory Hierarchy. 225-232
• 
  Sandra Johnson Baylor, Faye A. Briggs: The Effects of Cache Coherence on the Performance of Parallel PDE Algorithms in Multiprocessors. 233-236
• 
  David T. Harper III: Address Transformations to Increase Memory Performance. 237-241
• 
  B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen: The Cydram 5 Stride-Insensitive Memory System. 242-246

Regular and Systolic Arrays

• 
  Suresh C. Kothari, Heekuck Oh, Ethan Gannet: Optimal Designs of Linear Flow Systolic Architectures. 247-256
• 
  Zhijun Tong: The Optimal Assignment of Sequential Programs to a Pipelined Linear Processor Array. 257-260
• 
  Hee Yong Youn, Adit D. Singh: A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI. 261-265
• 
  Jorge L. Aravena, Ahmed El-Amawy: Time Optimal Operation of Heterogeneous Arrays. 266-269

Networks III

• 
  Hsing-Lung Chen, Nian-Feng Tzeng: Enhanced Incomplete Hypercubes. 270-277
• 
  David Nassimi: A Fault-Tolerant Routing Algorithm for BPC Permutations on Multistage Interconnection Networks. 278-287
• 
  David M. Koppelman, A. Yavuz Oruç: A Self-Routing Permutation Network. 288-295
• 
  Thomas Schwederski, Howard Jay Siegel, Thomas L. Casavant: Task Migration Transfers in Multistage Cube Based Parallel Systems. 296-305

Architecture Potpourri

• 
  Carla Schlatter Ellis, David Kotz: Prefetching in File Systems for MIMD Multiprocessors. 306-314
• 
  A. L. Narasimha Reddy, Prithviraj Banerjee: Performance Evaluation of Multiple-Disk I/O Systems. 315-318
• 
  Hiroshi Kadota, Katsuyuki Kaneko, Yuji Tanikawa, Tatsuo Nogi: VLSI Parallel Computer with Data Transfer Network: ADENA. 319-322
• 
  Abhaya Asthana, H. V. Jagadish, Boyd Mathews: Impact of Advanced VLSI Packaging on the Design of a Large Parallel Computer. 323-327